ECE 212 Logic Design (or equivalent) covering the basics of digital logic design, including combinational logic design, hand techniques for logic minimization, latches and flip-flops. Familiarity with digital system building blocks, including registers, adders, muxes, etc. Familiarity with the programming language C is desirable; or consent of instructor.
After completing this course, the student will be able to:
- Understand how modern digital systems are designed based around the use of hardware description languages, logic synthesis and mapping onto standard cell and field programmable logic.
- Understand non-logic-design issues in ASIC design, including timing, power, and verification.
- Know how to approach block level optimization in ASIC design.
- Demonstrate understanding of design in a major project.
- Discuss future trends in digital system design.
Homeworks & Online quizzes: 25%
Midterm Exam: 12%
Project Plan - Prelim Report: 3%
Project - Final Report: 35%
Final exam: 25%
Software Requirements: You need access to a Verilog simulator and a synthesis tool. NCSU will provide you remote access to Mentor Modelsim and Synopsys DC compiler, and a suitable ASIC library. To use those tools remotely you will need a high quality internet access and an Xwindows interface (Linux or Xwin32). Also some companies firewalls will block access to graphical tools like this. You can use comparable tools provided by your employer, including other simulators other synthesis tools, and suitable libraries. Unfortunately, there are no freeware or student version tools available that are suitable for this class.
Purchase is Optional:
M.D. Ciletti, “Advanced Digital Design with the Verilog HDL,” (Prentice Hall), 2011. ISBN 9780136019282. This text is a good language guide with numerous examples.
D.R. Smith and P.D. Franzon, "Verilog Styles for Synthesis," (Pearson Education [Prentice Hall]), 2000.
ISBN. 0-201-61860-5. The chapters on design, timing, test benches are lifted straight from this course.
W. Dally and R.C. Harting: “Digital Design: A Systems Approach”, (Cambridge), 2012, ISBN 0521199506
Thomas and Moorby, ``The Verilog Hardware Description Language'', 3rd edition, Kluwer Academic. ISBN 0-7923-9723-1.
S. Sutherland, S. Davidman, P. Flake, “System Verilog for Design” (Kluwer), 2006, ISBN 9780387333991.
S. Kilts, “Advanced FPGA Design”, (Wiley), ISBN 978-0-05437-6 H. Bhatnagar, “Advanced ASIC Chip Synthesis Using Synopsys Design Compiler, Physical Compiler, and PrimeTime”, ISBN 0-7923-7644-7.
Dr. Paul D. Franzon, Professor
Director, Electronics Research Lab
Director, Graduate Programs
Department of Electrical and Computer Engineering
443 MRC (Larry K. Monteith Engineering Research Center)
Campus Box 7911
NC State University
Raleigh, NC 27695-7911