3 Credit Hours

This course covers the technologies, techniques, and methodologies used to verify functional correctness of digital logic. SystemVerilog, IEEE-1800, is the language used in this course to create class based simulation environments that use object oriented programming techniques, constrained randomization, and functional coverage to find bugs in digital designs. This course is the prerequisite for ECE 748, “Advanced Verification using UVM”.

Prerequisite

ECE 564, ASIC and FPGA Design with Verilog, or equivalent.

Course Objectives

1. To make the student proficient in the industry standard language used for functional verification, SystemVerilog.
2. To give the student the ability to architect and implement layered, class based, simulation environments.
3. To prepare the student for learning the industry standard methodology used for functional verification, UVM.

Course Outcomes

By the end of the course students will be able to:

1. Verify complex digital designs at block and chip level, identifying the contained bugs, and closing functional coverage, using SystemVerilog.
2. Explain the purpose and design of base class packages used in functional verification.
3. Use a base class package to create layered test benches used in ASIC and FPGA Verification and their implementation using SystemVerilog.

Course Requirements

The course approach is similar to how the instructor teaches SystemVerilog to engineering professionals. All instructional material will be delivered during lectures. Lecture materials will include conceptual descriptions, examples, and sample code. Questions during lectures is recommended and encouraged. Instructional flow reflects typical verification development flow for production designs.
The course contains four projects. The projects build upon each other. The content created in the first project will be used in the second project. The content created in the second project will be used in the third project. The content used in the third project will be used in the fourth project. All concepts required for project development will be covered during lectures. Students will have approximately four weeks to complete each project. Projects will be done individually. Projects will reflect architectures and techniques typically used for ASIC and FPGA verification of production designs.
The course contains three tests. The first test will be held in week 4 or soon thereafter. The second test will be held in week 8 or soon thereafter. Test questions reflect typical interview questions on SystemVerilog. Therefore, tests are closed book and closed-notes.

Student Evaluation

Item	Contribution
Test1	10%
Test 2	10%
Test 3	10%
Project 1	15%
Project 2	25%
Project 3	15%
Project 4	15%
Total	100%

Textbook

SystemVerilog for Verification – A Guide to Learning the Testbench Features, Chris Spear, Greg Tumbush Springer, 2012.

ISBN 978-1-4614-0714-0, e-ISBN 978-1-4614-0715-7

Updated: 10/31/2025.